Programmable Integrated Circuits (ICs) are ICs that are user configurable and capable of implementing digital logic operations. There are several types of programmable ICs, including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture with sum-of-products logic, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs).
The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that are programmable to implement a portion of a larger logic function. The CLBs, IOBs and interconnect lines are configured by data stored in a configuration memory of the FPGA.
The reprogrammability of many programmable ICs makes them advantageous in many applications because it is possible to update (reconfigure) programmable logic by loading new configuration data, as compared to application-specific integrated circuits (ASICs), which would require replacement. The versatility of reprogrammable ICs is advantageous in applications such as aerospace where remote reconfiguration is preferred over physical replacement. However, many aerospace applications expose components to environments where radiation is present, which can cause single event upsets (SEUs) in configuration memory cells and result in the configured logic not operating as intended. In some instances, an SEU may have only a transient effect and may disappear.
Previous techniques to mitigate the affect of SEUs involve the use of triple modular redundancy (TMR). In these techniques three redundant copies of selected logic are implemented and operate in parallel. The output of each copy is analyzed by a majority voter to determine the correct value of the output. In addition to TMR, scrubbing may be employed to reconfigure the memory cells of the integrated circuit when an SEU is detected. However, triple modular redundancy is expensive as the circuit needs to be triplicated, which requires three times the circuit area of the single circuit.
The present invention may address one or more of the above issues.